Many applications in modern electronics require that continuous-time signals be converted to discrete signals for processing using digital computers and signal processors. Conventionally, this transformation is made using a method similar to converter circuit 5, illustrated in FIG. 1. Circuit 5 converts analog input 6 (i.e., both continuous in time and continuously variable) to discrete digital output 16 (i.e., both sampled in time and quantized in value) using lowpass filter 8, sample-and-hold circuit 10 (sampler), and quantizer 14. The instantaneous bandwidth of such a sampled system is limited by the Nyquist criterion to a maximum theoretical value equal to one-half the sample clock (fCLK) frequency (i.e., the Nyquist limit). Therefore, the purpose of lowpass filter 8, in circuit 5, is to reject frequencies above the Nyquist limit, so that discrete output 16 is not corrupted by errors related to aliasing. For this reason, filter 8 is often referred to in the prior art as an anti-aliasing filter. At time intervals determined by clock frequency 12, sample-and-hold circuit 10 captures the output value of anti-aliasing filter 8 (i.e., an analog signal), and holds that value while quantizer 14 uses a rounding operation to produce discrete-time, discretely-valued output 16 (i.e., a digital signal). The number of discrete levels in the rounding operation of quantizer 14 determines the conversion resolution, or maximum precision, associated with analog-to-digital converter circuit 5. Converter precision is often specified as an effective number of bits (ENOB), such that for Q levels in the rounding operation, the ENOB is less than or equal to log2(Q).
In general, the precision of an analog-to-digital converter (ADC) is less than log2(Q) because of impairments such as sampling uncertainty, or timing jitter, that degrade the accuracy of the sampling/quantization operation and reduce the quality of the conversion process. Although one source of sampling uncertainty is the inability of sample-and-hold circuit 10 to consistently capture signals on the transitions (i.e., rising and falling edges) of sample clock 12, a primary source of sampling jitter/uncertainty in conventional ADCs tends to be the sample clock source itself. The sample clock is produced by a circuit, often called an oscillator, which conventionally includes a network that is resonant at a particular frequency (i.e., a resonator). FIG. 2A is an exemplary conventional oscillator known as a Pierce oscillator. Sampling jitter/uncertainty results when the oscillator output frequency varies or drifts over time due to resonator instabilities, and/or other circuit imperfections. Fluctuations (perturbations) in oscillator output frequency and/or phase are generally classified according to the time scale over which the fluctuations occur. For example, rapid fluctuations in oscillator output frequency, such as those having periods on the order of nanoseconds to microseconds, produce what is referred to as short-term jitter, or high-frequency jitter (i.e., white phase noise). Conversely, slow fluctuations in oscillator output frequency, such as those having periods on the order of milliseconds to tenths of seconds, produce what is referred to as long-term jitter or low-frequency jitter (i.e., flicker-phase noise or white-frequency noise). Finally, extremely slow fluctuations in oscillator output frequency, such as those with periods on the order of seconds to many seconds, produce what is referred to as wander (i.e., flicker-frequency noise or random frequency walk). FIG. 2B provides a classification of clock frequency instability based on the rate of variation exhibited by the fluctuations in the oscillator output. As shown in FIG. 2B, low-frequency jitter and wander typically have greater magnitudes (i.e., are associated with larger deviations in desired frequency and time period) than high-frequency jitter.
To illustrate the effects of sampling jitter on an ADC, it is informative to consider first the case of a narrowband (sinusoidal) input signal, such as x(t)=Am·sin(ωmt+φm), with arbitrary amplitude (Am), arbitrary phase (φm), and angular frequency ωm<π·fCLK. Assuming infinite resolution (i.e., number of rounding levels Q→∞), the discrete-time output of the converter is given byŷk(n)=Am sin(ωmT·n+φm+ωm·φ),where the sampling interval T=1/fCLK and φ is a white, Gaussian noise sequence produced by sampling jitter (uncertainty) having power σφ2 and power spectral density N0 
      (                  i        .        e        .            ,                        N          0                =                              σ            φ            2                    /                      (                                          1                2                            ·                              f                                  C                  ⁢                                                                          ⁢                  L                  ⁢                                                                          ⁢                  K                                                      )                                )    .For the case where |φ|<<1, which is typical for high-precision clock sources, it is relatively straightforward for those skilled in the art to show thatŷ(n)≈Am·sin(ωmT·n+φm)+Am·cos(ωmT·n+φm)·(ωm·φ),where the first term in the above equation is the sampled input signal and the second term is noise introduced by sampling jitter. The power in the noise term increases with the square of the input angular frequency ωm according to
            P              Noi        ⁢                                  ⁢        se              =                  1        2            ·              A        m        2            ·              σ        φ        2            ·              ω        m        2              ,and this noise adds directly to the converter output to degrade conversion accuracy. Specifically, the effective resolution (i.e., ENOB) of a data converter degrades by 0.5 bits for every factor of two increase in output noise.
The jitter analysis above can be extended to the case of a broadband input signal by considering that any real, bandlimited signal can be approximated by a finite sum of sinusoids via a Fourier series. In analyzing the effects of sampling jitter, therefore, it is convenient to represent a broadband input signal (x), with bandwidth fB, as the sum of K sinusoids having arbitrary amplitude and arbitrary phase, where
            x      ⁡              (        t        )              =                  ∑                  k          =          0                          K          -          1                    ⁢                        A          k                ·                  sin          ⁡                      (                                                            ω                  k                                ⁢                t                            +                              ϕ                k                                      )                                ,and: (1) amplitude values Ak are uniformly distributed over the interval [−1, 1]; (2) phase values φk are uniformly distributed over the interval (−π, +π]; and (3) angular frequency values ωk are uniformly distributed over the interval [0, 2π·fB] (i.e., ω0=0 and ωK−1=2π·fB). Again assuming infinite resolution (i.e., number of rounding levels Q→∞), the discrete-time output of the converter is given by
                              y          ^                k            ⁡              (        n        )              =                            ∑                      k            =            0                                K            -            1                          ⁢                              A            k                    ⁢                      sin            ⁡                          (                                                                    ω                    k                                    ⁢                                      T                    ·                    n                                                  +                                  ϕ                  k                                +                                                      ω                    k                                    ·                  φ                                            )                                          ≈                                    ∑                          k              =              0                                      K              -              1                                ⁢                                    A              k                        ·                          sin              ⁡                              (                                                                            ω                      k                                        ⁢                                          T                      ·                      n                                                        +                                      ϕ                    k                                                  )                                                    +                              ∑                          k              =              0                                      K              -              1                                ⁢                                    A              k                        ·                          cos              ⁡                              (                                                                            ω                      k                                        ⁢                                          T                      ·                      n                                                        +                                      ϕ                    k                                                  )                                      ·                          (                                                ω                  k                                ·                φ                            )                                            ,where the second term, which is the output noise introduced by sampling jitter, has power
      P    Noise    =                    1        2            ·      K      ·      E        ⁢                  {                  A          k          2                }            ·              σ        φ        2            ·              1        K            ·                        ∑                      k            =            0                                K            -            1                          ⁢                              ω            k            2                    .                    As K→∞ the power in the noise term converges to
            P      Noise        =                  1        3            ·              σ        S        2            ·              σ        φ        2            ·                        (                      2            ⁢                          π              ·                              f                B                                              )                2              ,where σS2 is the input signal power. Therefore, the extent to which sampling jitter degrades conversion accuracy is proportional to the square of the input signal bandwidth fB.
As a result of the above analysis, the present inventor has identified a need for minimizing the effects of sampling jitter in data converter circuits, particularly those that are required to process input signals with high-frequency content (i.e., large ωk), or wide bandwidth (i.e., large fB). To overcome the processing speed limitations of electronic circuits, high-frequency converters conventionally employ an arrangement where multiple, distinct converters are operated in parallel (i.e., parallel processing). Conventional parallel processing arrangements include time-interleaving (time-slicing) converters and frequency-interleaving (frequency-slicing) converters. For interleaving in time, a high-speed sample clock is decomposed into multiple, lower-speed sample clocks (i.e., subsampling clocks) at different phases (i.e., phase offsets). Each converter in the time-interleaving array is clocked with a different clock phase, such that the conversion operation is distributed in time across multiple converters. Distributing processing operations across time is a technique that often is referred to as polyphase decomposition in the prior art. While converter #1 is processing the first sample, converter #2 is processing the next sample, and so on.
For interleaving in frequency, the total bandwidth of the continuous-time signal is uniformly divided into multiple, narrowband segments (i.e., sub-bands). Processing a wideband signal as multiple narrowband segments is a technique that often is referred to in the prior art as frequency (spectral) decomposition or decomposition in frequency. Each parallel processing branch converts one narrowband segment, and all the converter processing branches operate from a single, common sampling clock. One representative implementation of a frequency-interleaving ADC is circuit 30A, shown in FIG. 3A, where the individual bands are separated out and downconverted to baseband. More specifically, input signal 31 is provided to a set of multipliers 32 together with the band's central frequencies 33-35. The resulting baseband signals are then provided to a set of identical, lowpass filters 36 that are designed to spectrally decompose the input signal (i.e., a process conventionally referred to as signal analysis), in addition to minimizing aliasing. Each such filtered baseband signal is then digitized by sampling/quantization circuits 40A, digitally upconverted by multipliers 42, using digitized sinusoids 43-45 (or alternatively simply upsampled), and then bandpass filtered (i.e., within reconstruction filters 46-48) in order to restore the input signal to its previous frequency band (i.e., a process conventionally referred to as signal synthesis). Finally, the individual bands are recombined within a set of one or more adders 49. Instead of operating at a sampling frequency equal to twice the bandwidth of the input signal, each converter 40A in the interleaved array is able to operate at a lower sampling frequency equal to twice the bandwidth of each subdivided, downconverted band (i.e., the portion of the input signal intended to be converted by the respective processing branch).
Frequency-interleaving converter circuit 30A, illustrated in FIG. 3A, is typically referred to as a frequency-translating hybrid (FTH) architecture. See Mazlouman, S., “Digital Compensation Techniques for Frequency-Translating Hybrid Analog-to-Digital Converters”, IEEE Transactions on Instrumentation and Measurement, Volume 60, Number 3, 2011. An alternative, conventional frequency-interleaving converter, first described by Petraglia and Mitra in 1990, is the hybrid filter bank (HFB) converter circuit 30B, shown in FIG. 3B. See Petraglia, A., “High Speed A/D Conversion using QMF Filter Banks”, Proceedings: IEEE International Symposium on Circuits and Systems, 1990. The operation of the HFB converter is similar to that of the FTH converter, except that input signal 31 is provided to a set of analog, bandpass filters 36-38 (i.e., conventionally referred to as signal analysis filters) for spectral decomposition, before being provided to multipliers 32 for downconversion to baseband using the band's central frequencies 33-35. The analog input (bandpass-decomposition) filters are conventionally designed for minimum spectral overlap (i.e., non-overlapping passbands), with preferred bandwidths of fCLK/2M, where fCLK is the converter sample-rate frequency and M is the number of parallel processing branches. See Velazquez, S., “Design of Hybrid Filter Banks for Analog/Digital Conversion”, IEEE Transactions on Signal Processing, Volume 46, Number 4, 1998. As in the FTH approach, each converter 40A in the interleaved array of the HFB converter operates at a sampling frequency equal to twice the bandwidth of each subdivided, downconverted band (i.e., the portion of the input signal intended to be converted by the respective processing branch). Conventionally, the FTH approach is preferred over the HFB approach because: (1) matched lowpass-decomposition filters are easier to implement than matched bandpass-decomposition filters, (2) filtering after downconversion ensures minimal spectral overlap between sub-bands; and (3) filtering prior to digitizing reduces errors due to aliasing. See Ding, G., “Frequency-Interleaving Technique for High-Speed A/D Conversion”, Proceedings: IEEE International Symposium on Circuits and Systems, 2003. The present inventor has discovered, however, that since the FTH approach employs no bandlimiting prior to the downconversion operation, intermodulation distortion that is introduced by the input multipliers can degrade conversion accuracy.
A variation on the conventional hybrid filter bank (HFB) converter is the multiband delta-sigma (MBΔΣ) converter circuit 30C, shown in FIG. 3C. See Aziz, P., “Multi Band Sigma Delta Analog to Digital Conversion”, IEEE International Conference on Acoustics, Speech, and Signal Processing, 1994. This approach attempts to solve the difficulties associated with implementing matched bandpass-decomposition (analysis) filters by eliminating them completely. And unlike conventional FTH and HFB converters, the MBΔΣ converter performs no spectral (frequency) decomposition in the analog domain. The input signal 31 instead is provided directly to the sampling/quantization circuits 40B, which consequently prevent aliasing errors by sampling at twice the bandwidth of the input signal, rather than at twice the bandwidth of a subdivided band. The present inventor has discovered that a primary disadvantage of MBΔΣ approach is increased sensitivity to timing jitter, due to the presence of wideband signals at the inputs of each sampling/quantization circuit (i.e., no analog bandlimiting prior to sampling and quantization). The present inventor also has discovered that another disadvantage of frequency decomposition in the analog domain, as in FTH and HFB converters, is that the practical (e.g., manufacturing) constraints associated with analog bandpass filter quality factor (i.e., quality factor Q, defined as the ratio of filter center frequency to filter bandwidth) limits the number of processing branches to about 25 to 30, a number which may be insufficient for realizing desired bandwidth and conversion-accuracy targets.
Although, conventionally, frequency-interleaving converters are considered to be less sensitive to timing jitter than time-interleaving converters, as a result of downconversion to baseband and use of a common sampling clock (Ding 2003), timing jitter is a problem for any converter that processes high-frequency input signals. Conventional methods for reducing timing jitter generally attempt to attenuate the short-term jitter (i.e., white phase noise) of the sampling clock source, ignoring longer-term jitter and drift. See Smilkstein, T., “Jitter Reduction on High-Speed Clock Signals” (PhD Thesis), University of California, Berkeley, 2007. These conventional methods typically involve improving the stability of the clock oscillator itself, for example using high-precision atomic or quartz resonators, or involve use of phase-locked loop (PLL) techniques (Smilkstein, 2007) to slave the frequency of a relatively stable oscillator (i.e., atomic or quartz) to the average frequency of a relatively unstable or noise-corrupted clock source.
Circuit 50, illustrated in FIG. 4A, is an exemplary PLL of the type conventionally used for reducing the high-frequency jitter of a sampling clock source. In circuit 50, the output phase of clock source 52, which has been corrupted by noise, is compared to the output phase of low-jitter, controlled oscillator 60 within phase detector 56. The phase difference 57 (i.e., phase error) between the noisy (high-jitter) clock source and the precision oscillator is lowpass filtered, by loop filter 58, to produce control signal 59. Control signal 59 adjusts the frequency of controlled oscillator 60 to match the average frequency of noisy clock source 52. A frequency divider (e.g., divider 62) can be included in the feedback path of the PLL such that the frequency (fOSC) at PLL output 61 equals fOSC=D·f0, where f0 is the nominal frequency of the noisy clock source and D is the frequency-input to frequency-output ratio (i.e., divide ratio) of the divider.
The jitter transfer function of circuit 50 is the frequency response from output 53 of noisy oscillator 52, to output 61 of the PLL. For phase detector 56 having gain KD, for controlled oscillator 60 having gain (i.e., modulation sensitivity) KV, and for loop filter 58 having second-order, lag-lead response
            H      ⁡              (        s        )              =                  1        +                  β          ·          s                            α        ·        s              ,the jitter transfer function, HJTF, has a lowpass response given by
            H      JTF        =                  ω        n        2                    1        +                  2          ⁢                      ζω            n                          +                  ω          n          2                      ,where the PLL natural frequency ωn=√{square root over (KD·KV/α)} and the PLL damping factor
  ζ  =            1      2        ·          ω      n        ·          β      .      For reference, the jitter transfer function for PLL circuit 50 is plotted in FIG. 4B. As illustrated in FIG. 4B, jitter that fluctuates at a rate greater than ωn is attenuated by the PLL. The clock signal at the output of the PLL will be more stable than the output of noisy clock source 52, when: (1) controlled oscillator 60 has very low jitter (i.e., the output of oscillator 60 is relatively stable) and (2) ωn, is lower than the fluctuation rate (frequency) for the dominant source(s) of jitter (e.g., white frequency, flicker phase, white phase) on noisy clock source 52.
Conventional methods for estimating the instantaneous frequency drift (i.e., and resulting jitter) of oscillators also exist, but rather than being used to compensate for sampling uncertainty and jitter-related system impairments, these methods are conventionally used for the characterization of oscillator phase noise, for the coarse automatic frequency control/calibration of receivers, and/or for the demodulation of angle modulated (FM/PM) carriers. See Hewlett Packard Product Note 11729C-2, “Phase Noise Characterization of Microwave Oscillators: Frequency Discriminator Method”, 1985; Lee, S. T., et al., “A Quad Band GSM GPRS Transmitter with Digital Auto Calibration”, IEEE Journal on Solid-State Circuits, 2004; and Gheidi, H., et al., “An Ultra-Broadband Direct Demodulator for Microwave FM Receivers”, IEEE Transactions on Microwave Theory and Techniques, 2011. These conventional methods include the conventional oversampling discriminator, similar to that described in Beards, D., “An Oversampling Delta-Sigma Frequency Discriminator”, IEEE Transactions on Circuits and Systems II, 1994; and the conventional delay-line discriminator, similar to circuit 70 illustrated in FIG. 5A. Referring to conventional discriminator circuit 70, the output x of mixer 75 is equal to
                    x        =                ⁢                              K            M                    ·                      cos            ⁡                          (                              2                ⁢                                  π                  ·                                      (                                                                  f                        0                                            +                                              Δ                        ⁢                                                                                                  ⁢                        f                                                              )                                    ·                  t                                            )                                ·                      cos            ⁡                          (                              2                ⁢                                  π                  ·                                      (                                                                  f                        0                                            +                                              Δ                        ⁢                                                                                                  ⁢                        f                                                              )                                    ·                                      (                                          t                      -                      T                                        )                                                              )                                                              =                ⁢                                            1              2                        ⁢                                          K                M                            ·                              cos                ⁡                                  (                                      2                    ⁢                                          π                      ·                                              (                                                                              f                            0                                                    +                                                      Δ                            ⁢                                                                                                                  ⁢                            f                                                                          )                                            ·                      T                                                        )                                                              +                                    1              2                        ⁢                                          K                M                            ·                                                                      ⁢                  cos          ⁡                      (                                          4                ⁢                                  π                  ·                                      (                                                                  f                        0                                            +                                              Δ                        ⁢                                                                                                  ⁢                        f                                                              )                                    ·                  t                                            -                              2                ⁢                                  π                  ·                                      (                                                                  f                        0                                            +                                              Δ                        ⁢                                                                                                  ⁢                        f                                                              )                                    ·                  T                                                      )                              where: (1) KM is a constant that depends on the peak-to-peak output voltage of mixer 75; (2) input signal 71 has a nominal frequency equal to f0; (3) the nominal frequency f0 deviates (fluctuates) by an amount equal to Δf; and (4) delay element 72 has a delay equal to T. In essence, delay element 72 produces a frequency-dependent phase shift equal to 2π·(f0+Δf)·T. Conventionally, delay element 72 is adjusted for a delay of
      T    =                  1        4            ·                        (                                    2              ·              k                        +            1                    )                /                  f          0                      ,where k is an integer, such that the signals at the inputs of mixer 75 are in quadrature, and the corresponding variation in amplitude (Δy) at the output of lowpass filter 78 is equal to
            Δ      ⁢                          ⁢      y        =                            ±                      K            M                          ·                  sin          ⁡                      (                          2              ⁢                              π                ·                Δ                            ⁢                                                          ⁢                              f                ·                T                                      )                              ≈                        ±          2                ⁢                  π          ·                      K            M                    ·          T          ·          Δ                ⁢                                  ⁢        f              ,for T·f<<1. Thus, the signal level Δy at the output of discriminator 70 is periodic in frequency with period 1/T; and is approximately proportional to the instantaneous frequency deviations Δf with a constant of proportionality equal to 2π·KM·T. It should be noted that delay element 72 is typically made as long as practical (i.e., the integer k is made as large as practical) to increase the sensitivity of the conventional discriminator to small deviations (fluctuations) in frequency.
Conventional methods for estimating instantaneous frequency deviation operate on the principle of slope detection, a process in which frequency fluctuations (i.e., frequency modulation or FM) are converted to amplitude fluctuations (i.e., amplitude modulation or AM) that can be recovered using an envelope detector (i.e., circuitry 76 in FIG. 5A). For example, frequency responses (i.e., curves 79A&B) for a conventional delay-line discriminator are shown in FIG. 5B, where: (1) curve 79A is a plot of output magnitude versus frequency deviation for a conventional discriminator with delay T=1 microsecond; and (2) curve 79B is a plot of output magnitude versus frequency deviation for a conventional discriminator with delay T=1 nanosecond. As curves 79A&B illustrate, the discriminator has a linear response (i.e., constant slope) for a range of input frequency deviations. With proper tuning of the discriminator delay T, the linear region can be made to bound the intended dynamic range of operation, such that an input signal of constant amplitude produces an output signal whose amplitude (magnitude) is linearly dependent on input frequency deviation. A comparison of curves 79A&B illustrates that the linear region can be extended by reducing the discriminator delay T, at the expense of reducing the sensitivity (i.e., reducing the magnitude) of the discriminator output to small deviations in frequency. Operation of the discriminator at frequency deviations that lie outside of this linear region conventionally is avoided because: (1) nonlinearities (i.e., slope changes) in the output response can introduce harmonic distortion that degrades the accuracy of the conversion from frequency variation (deviation) to amplitude variation; and (2) the periodic response of the discriminator output creates an ambiguity region where the relationship between frequency variations and amplitude variations is not a one-to-one function. More specifically, a region of ambiguity occurs for input frequency deviations greater than Δf=½T.
Conventional apparatuses for estimating instantaneous frequency drift suffer from design limitations that make them inadequate and/or impractical for use in the correction of sampling uncertainty/jitter. These design limitations can result from a combination of: (1) the inability to resolve small frequency fluctuations due to the relative insensitivity of conventional delay-line discriminators (i.e., inability to resolve deviations where Δf<<1/T, such that 2π·T·Δf is approximately zero); (2) the inability to resolve large frequency fluctuations due to ambiguities resulting from the periodic response of conventional delay-line discriminators (i.e., deviations where Δf>½T, such that 2π·T·Δf is larger than π radians); and/or (3) the inability to make accurate measurements due to the susceptibility of oversampled frequency discriminators to the errors introduced by sampling clock jitter (see Kwon, J., et al., “Impact of Sampling Clock Phase Noise on ΣΔ Frequency Discriminators”, IEEE Transactions on Circuits and Systems II, 2007). The above limitations generally constrain the use of conventional discriminators to narrowband applications, such as the demodulation of FM signals and/or the measurement of low-frequency phase noise, and preclude their use in jitter detection and compensation applications, which require both wide bandwidth and high estimation sensitivity/accuracy. Although conventional methods for extending the usable range of delay-line discriminators exist, these methods typically rely on the integration of multi-tiered delay elements, and are impractical for many applications, including those targeting a small form factor. See Sullivan, T., “Gauging Limitations on DFD Performance”, Microwave and RF Magazine, November 2005; and Thorton, M. J., “Frequency Discriminators for Broadband Applications”, Proceedings of Automated RF & Microwave Measurement Society“, 2011.
In addition to methods for estimating instantaneous frequency drift, conventional techniques for sample-rate conversion can be used to adjust/change the sampling rate and phase of discrete-time signals (i.e., in order to obtain a new discrete-time representation of an underlying continuous-time signal). Sample-rate conversion is a process that sometimes is referred to in the prior art as digital interpolation, or digital resampling, and is based on oversampling structures, such as Farrow interpolators, which fabricate new data samples from existing/known data samples using curve-fitting with polynomial functions (i.e., polynomial estimation). See Farrow, C. W., “A Continuously Variable Digital Delay Element”, IEEE International Symposium on Circuits and Systems, 1988. Conventionally, these techniques are used to synchronize two or more oscillators in oversampled systems. See Gardner, Floyd M., “Interpolation in Digital Modems I—Fundamentals”, IEEE Transactions on Communications, 1993; and Gardner, Floyd M., “Interpolation in Digital Modems II—Implementation and Performance”, IEEE Transactions on Communications, 1993. Adapting these conventional structures for use in Nyquist-sampled systems, or for correcting the instantaneous frequency drift (i.e., and resultant jitter) of a local oscillator, however, has not been contemplated in the prior art.
FIG. 6A illustrates a conventional first-order polynomial estimator (i.e., interpolator 80A) that fabricates new data samples (yn) from existing data samples (xn) according to the linear functionyn=xn·(1+Δn)−xn−1·Δn,which is realized using digital delay (i.e., register 83A), addition (i.e., adders 82A&B), and multiplication (i.e., multiplier 84A) operations. The parameter Δn is sometimes referred to as the curve-fit interpolant (i.e., an independent control variable that specifies the unit-interval offset between a current sample-time instant and a new sample-time instant). With respect to the above equation, more negative interpolant values (e.g., Δn→−1) advance the sample-time instant (i.e., shift sampling to an earlier point in time) and less negative interpolant values (e.g., Δn→0) delay the sample-time instant (i.e., shift sampling to a later point in time). FIG. 6B illustrates a conventional second-order polynomial estimator (i.e., interpolator 80B) that, based on interpolant Δn, fabricates new data samples (yn) from existing data samples (xn) according to the parabolic function
            y      n        =                            x          n                ·                  (                                                    1                2                            ⁢                              Δ                n                2                                      +                                          1                2                            ⁢                              Δ                n                                              )                    +                        x                      n            -            1                          ·                  (                      1            -                          Δ              n              2                                )                    +                        x                      n            -            2                          ·                  (                                                    1                2                            ⁢                              Δ                n                2                                      -                                          1                2                            ⁢                              Δ                n                                              )                      ,which also is realized using digital delay (i.e., registers 80B&C), addition (i.e., adders 82C-G), and multiplication (i.e., multipliers 84B&C) operations. For the above second-order function, negative interpolant values (e.g., Δn<0) advance the sample-time instant (i.e., shift sampling to an earlier point in time) and positive interpolant values (e.g., Δn>0) delay the sample-time instant (i.e., shift sampling to a later point in time).
For sufficient bandlimiting (i.e., or equivalently, sufficient oversampling), the relationship between a discrete value at one sample-time instant, and a discrete value at a different sample-time instant (i.e., resulting from a different sampling rate or phase), is well approximated over a sample-time interval by a polynomial function. Specifically, the accuracy of conventional polynomial estimation depends on the extent to which the sample-rate frequency (fS) of a discrete-time signal exceeds the maximum frequency component (fN) of that discrete-time signal. More specifically, the present inventor has determined that the approximate accuracy (i.e., relative error) of a parabolic (i.e., second-order polynomial) estimation improves according to the cube of the ratio fS/fN, such that for every factor of two increase in the ratio fS/fN, the accuracy (ε) of the estimation improves by a factor of about 8, or
  ɛ  ≈            k                        (                                    f              S                        /                          f              N                                )                3              .  However, the present inventor has discovered that at oversampling ratios of fS/fN<8, the accuracy of conventional polynomial estimation (interpolation) methods becomes severely degraded. Therefore, improved interpolation methods are required for high-speed conversion and signal processing applications, which preferably are Nyquist-sampled, and which preferably operate with high-accuracy at oversampling ratios as low as fS/fN=2 (i.e., no oversampling).
The performance of conventional analog-to-digital converters is significantly degraded by random sampling jitter, particularly at high sampling rates. The performance of conventional time-interleaved converters is also limited by the deterministic sampling jitter, e.g., resulting from imperfections (i.e., skew) in the phase offsets applied to each of the subsampling clocks. In addition, conventional methods for jitter attenuation and sample-rate conversion are only marginally suitable for use in correcting the instantaneous frequency drift (i.e., and resultant jitter) of a sampling clock source. For example, the conventional PLL-based methods for jitter attenuation require controlled oscillators with high stability, and as illustrated by the exemplary jitter transfer function in FIG. 4B, they are useful only for reducing the high-frequency jitter (i.e., short-term jitter) of a noise-corrupted clock source. More specifically, the present inventor has determined that conventional, PLL-based jitter attenuation methods have limited utility in converter applications due to disadvantages that include: (1) a tunable, high-precision oscillator generally cannot accommodate the wide range of conversion rates at which a converter typically needs to operate; (2) overall timing jitter is not reduced significantly because timing jitter tends to be dominated by low-frequency jitter, as illustrated in FIG. 2B (i.e., low-frequency jitter has higher power density than high-frequency jitter); and (3) the cost and complexity may be prohibitively large because the high-precision resonators needed to implement the controlled clock source cannot be integrated onto silicon devices using conventional methods. In addition, conventional methods for frequency drift estimation and sample-rate conversion are not accurate or precise enough to support signal processing applications that require both wide bandwidth (e.g., Nyquist sampling) and high-accuracy. For these reasons, improved apparatuses and methods are needed for reducing the performance degradation caused by timing jitter, particularly in converter applications where high-frequency input signals are processed.